If you have any other question about our products or services, please do not hesitate to contact us. You can do so through the Contact form or directing an email to the appropriate department in the Contact section.
What are the licensing restrictions?
An obvious restriction that applies and is common to the IP industry is that the licensee may not resell the IP core itself unless as part of another system. Our license is based, and very similar to, Xilinx SignOnce's IP license. This license model is really very open and convenient for both parts.
If you have any questions about the license or how it would apply in your specific situation, please do not hesitate to contact us.
How are your cores licensed?
VISENGI's IP cores are licensed on two categories, to best suit the client's needs and leverage the cost. Licenses are for unlimited projects and with no royalties:
- Netlist format (valid for only one type of FPGA)
- Source code format (valid for any FPGA/ASIC)
Do I have to generate any internal cores (RAM, FIFO, etc.) to be able to synthesize an IP core?
No. Any needed RAMs, ROMs, FIFOs, etc. are supplied as inferable cores in the form of VHDL files. This is the most convenient format, as it assures the most efficient implementation and best usability (it is vendor independent) than any pregenerated core form.
Are there any royalty fees associated with the use of your cores?
We license our cores on a one time fee basis, independent of your intended use or production volume.
What kind of technical support do you offer?
We are proud to offer our clients a top-notch technical support. As such, the client will be able to count on our engineers to work side by side with his team in the development process, up to the successful integration of VISENGI's IP cores into the final system. It is only at this point that we feel our objective to be accomplished.
What does source code format mean?
Source code format is a fully synthesizable VHDL code in a readable form, letting the licensee use the core without restrictions in any FPGA or ASIC.
What does Netlist format mean?
A Netlist is a precompiled and technology/vendor dependent form of IP core delivery for use in one family of FPGAs. Examples of different FPGA families are Cyclone V, Spartan-6, Zynq 7xxx, Stratix IV, Artix-7, etc. When a client chooses this format, the intended FPGA family name is sent to us and a Netlist is generated with the appropriate tool. The client will receive this Netlist file along with the documentation and full implementation guidelines to use it.
The downside of this format is that it can be synthesized only for one family of FPGA devices. Retargeting it to another FPGA family will imply an extra fee.
What Hardware description language (HDL) is used in the source code?
At VISENGI we base our developments in the VHDL language, defined in IEEE standard 1076, which lets us implement our solutions at the lowest level while meeting the strictest time to market requirements.