This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. Its main features are:

  • Baseline DCT compression according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard.
  • JFIF 1.02 standard file header.
  • Drag'n'drop IP block for Xilinx Vivado Block Design and Altera Quartus Qsys.
  • Constant throughput: 2 compressed pixels every 3 clock cycles
  • Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
  • Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
  • Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
  • Optional optimized pixel input mode to boost shared memory efficiency.
  • Optional SW control of the IP core configuration registers (sample source code provided)
  • On-the-fly selectable quality level/compression ratio from 1 to 100 before every compression.
  • Selectable JPG chroma subsampling (4:4:4, 4:2:2, 4:2:0), independent of input subsampling.
  • Unlimited image resolution (up to 64K x 64K as per JPEG spec.).
  • Support for RGB and YCbCr input pixels' color space
  • Optional SW modules: Comment insertion support, Motion JPEG .avi format support.
  • Unlimited Restart markers support.
  • ASIC: On ASIC TSMC 0.13G process technology over 166 Mpix/s (>250 MHz)

Quotation Request

If you are looking for HDR (up to 36bpp) you may be interested in VISENGI's JPEG Extended Encoder IP Core...

You may also be interested in VISENGI's M/JPEG Decoder IP Core...

VISENGI JPEG CODEC Broadcast System Demo


The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.

The input/output interfaces of the JPEGE IP core are the following:

  • Configuration Interface: AXI-Lite slave with a 32 bits interface to control all the necessary parameters of encoding.

  • Data I/O Interface: AXI3/4 Master interface with a data width of 64 bits for reading input pixels and writing .JPG files from/to memory. Optional AXI4-Stream pixel input interface and AXI4-Stream .JPG file output.

  • Interrupt output: A rising-edge interrupt is available, signaling when an image has been processed.

Quality Levels

In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image (requires a fast connection) in order to see the final compressed image (real output from the JPEG encoder core at chroma subsampling 4:4:4 (best quality)) and compression ratio.

Quality Level(1-100):


File Size: bytes

Compression Ratio: : 1


The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform, please use the search box in the "Resource Usage" section below to find your FPGA. The real throughput, in compressed pixels per second, will be the Maximum Frequency (in Hz) divided by three and then multiplied by two.

In case your application does need a much higher quality level, you may choose to compress images using a better chroma subsampling than 4:2:0. This will yield a better PSNR (Peak Signal to Noise Ratio) at the expense of compression ratio (bits per pixel). In the following table the choice is summarized with real quantities of PSNR and bpp for a quality ratio of 85 (the throughput depends only on the chroma subsampling) in a Virtex-5 with speed grade 3 and for the particular case of the colorful image used.

Throughput vs. Quality per Chroma Subsampling
Chroma SubsamplingPSNR @ Q=85Bits per Pixel @ Q=85Pixels / Cycle
4:4:433.5 dB3.81 / 3
4:2:2 Horizontal32.1 dB3.21 / 2
4:2:2 Vertical31.3 dB3.21 / 2
4:2:030.9 dB2.82 / 3

For a comparison of the slight visual difference among the chroma subsamplings, you can take a look at the next gallery section, where each image has been compressed at a different chroma subsampling and with Q=100 to preserve the differences.

The following two tables show a comparison of the aforementioned PSNR and Bits per Pixel as a function of the Quality ratio for each of the chroma subsamplings (Legend: Blue is 4:4:4, Red is 4:2:2 Horizontal, Green is 4:2:2 Vertical and Magenta is 4:2:0). Note that the PSNR difference between 4:2:2 Horizontal and 4:2:2 Vertical depends greatly on the objects in the image. The large difference with 4:4:4 is explained by the scale of the various colored objects in this particular image, which helps underscore the chroma subsampling differences.

Please note that the values shown are completely dependent on the image compressed.

To make valid comparisons you must use the same quality demanding image used here (download).

If you would like to test the outstanding quality of VISENGI's JPEG encoder, please send us your test images and we will gladly perform and return to you the results.

Resource Usage

In the next table you can find the synthesis results several FPGA vendors and families in which the core may be fitted. Please note that, since our designs are vendor and device independent, if your exact FPGA can not be found but it has enough resources compared to another FPGA, then it will doubtlessly also fit. In any case, if you would like to know the precise and up to date synthesis results for your specific FPGA or for ASIC targets, please contact us with your specific target.

VendorFamilySpeedRegsLUTs/ALMsDSPsBRAMs/MbitsMax. Freq.Throughput1080p FPS
VendorFamilySpeedRegsLUTs/ALMsDSPsBRAMs/MbitsMax. Freq.Throughput1080p FPS
XilinxArtix-7-34565810188161 MHz107 Mpix/s1080p50
XilinxKintex-7-34584806288212 MHz141 Mpix/s1080p67
XilinxZynq-34546800788188 MHz125 Mpix/s1080p60
XilinxSpartan-6-344708007131194 MHz62 Mpix/s1080p30
XilinxVirtex-6-34537807588210 MHz140 Mpix/s1080p66
XilinxVirtex-5-25268756989173 MHz115 Mpix/s1080p54
AlteraCyclone IVC64966103946109 Kbit129 MHz86 Mpix/s1080p40
AlteraCyclone VC65152438413109 Kbit140 MHz93 Mpix/s1080p44
AlteraArria VI35079438013109 Kbit183 MHz122 Mpix/s1080p58
AlteraArria 10I24840431813109 Kbit243 MHz162 Mpix/s1080p77
AlteraStratix IVI1439347606109 Kbit201 MHz134 Mpix/s1080p63
AlteraStratix VC14902438213109 Kbit252 MHz168 Mpix/s1080p80

Methodology notes:

  • Synthesis results were obtained using the freely available versions of Xilinx ISE/Vivado and Altera Quartus environments.

  • Maximum frequency is that reported by Synthesis for Xilinx ISE, and by TimeQuest's Slowest V/T model for Altera Quartus.

  • Throughput (subsampling 4:2:0) is calculated as: Max. frequency x 2 pixels encoded / 3 cycles.

  • 1080p FPS is given just as an example, resolution is unlimited.

  • Resource usage is subject to small changes due to further developments in quality/compression ratio.


Included with the core is:

Quotation Request

For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.