Features
VISENGI's Advanced Encryption Standard (AES) IP core provides AES-128, AES-192, and AES-256 encryption and decryption, as per FIPS-197, with a shockingly small resource usage, while allowing a large operating frequency.
The IP core's main features are:
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AES algorithm following Federal Information Processing Standards 197 (FIPS PUB 197).
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Constant encryption/decryption throughput, depending only on key size:
- AES128 (128 bits key): 77 cycles per 128 bits of data (1.66 Mbps/MHz)
- AES192 (192 bits key): 91 cycles per 128 bits of data (1.40 Mbps/MHz)
- AES256 (256 bits key): 105 cycles per 128 bits of data (1.21 Mbps/MHz)
Low latency one-time key expansion (<100 cycles) on all modes' start-up.
ECB block cipher mode of operation, quick adaptability to any mode (CBC, CTR, …).
Extremely simple FIFO-like 32 bits wide I/O.
Automatic key-length (AES128/AES192/AES256) inference.
The data interfaces used are simple FIFO-like with minimal control bits. The key size (AES128/192/256) is automatically inferred from the number of 32 bits words input when a new key is supplied (4, 6, or 8 cycles).
The input/output interfaces of the AES IP core are divided in three different parts:
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Control Interface: control bit to indicate encryption or decryption.
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Input Interface: shared 32 bits bus for both supplying a key and user data to encrypt/decrypt. It is a simple FIFO interface with a ready output and a data valid input.
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Output Interface: simple 32 bits sequential output of the encrypted/decrypted data.
For user-connection's convenience this IP core is designed with 32 bits wide buses. Hence, the AES' native blocks of 128 bits are input as 4 words of 32 bits one after the other, without pauses in between. The same is expected for the keys of size 128 bits (4 contiguous words of 32 bits), 192 bits (6 words), and 256 bits (8 words).
Resource Usage
In the next table you can find the synthesis results several FPGA vendors and families in which the core may be fitted. Please note that if your exact FPGA can not be found but it has enough resources compared to another FPGA, then it will doubtlessly also fit. In any case, if you would like to know the precise synthesis results for your specific FPGA or for ASIC targets, please contact us with your specific target.
| Vendor | Family | Speed | Regs | LUTs | BlockRAMs | Max. Freq. | Throughput |
|---|---|---|---|---|---|---|---|
| Vendor | Family | Speed | Regs | LUTs | BlockRAMs | Max. Freq. | Throughput |
| Xilinx | Virtex-6 | -1 | 585 | 1075 | 1 | 314 MHz | 521 Mbps |
| Xilinx | Virtex-5 | -1 | 588 | 1057 | 1 | 271 MHz | 450 Mbps |
| Xilinx | Virtex-4 | -12 | 684 | 2092 | 1 | 262 MHz | 435 Mbps |
| Xilinx | Zynq | -1 | 585 | 1063 | 1 | 300 MHz | 498 Mbps |
| Xilinx | Zynq | -3 | 585 | 1059 | 1 | 414 MHz | 688 Mbps |
| Xilinx | Artix-7 | -1 | 586 | 1112 | 1 | 252 MHz | 418 Mbps |
| Xilinx | Artix-7 | -3 | 585 | 1113 | 1 | 346 MHz | 575 Mbps |
| Xilinx | Kintex-7 | -1 | 585 | 1061 | 1 | 335 MHz | 556 Mbps |
| Xilinx | Kintex-7 | -3 | 585 | 1066 | 1 | 454 MHz | 754 Mbps |
| Xilinx | Spartan-6 | -2 | 592 | 1117 | 1 | 167 MHz | 277 Mbps |
| Xilinx | Spartan-6 | -3 | 590 | 1117 | 1 | 192 MHz | 319 Mbps |
| Xilinx | Spartan-3A DSP | -4 | 593 | 2176 | 1 | 139 MHz | 231 Mbps |
| Xilinx | Spartan-3A DSP | -5 | 595 | 2174 | 1 | 171 MHz | 284 Mbps |
| Xilinx | Spartan-3A | -4 | 593 | 2176 | 1 | 139 MHz | 231 Mbps |
| Xilinx | Spartan-3A | -5 | 595 | 2174 | 1 | 171 MHz | 284 Mbps |
| Altera | Cyclone III | C7 | 713 | 2307 | 2048 bits | 182 MHz | 302 Mbps |
| Altera | Cyclone IV | C6 | 713 | 2307 | 2048 bits | 189 MHz | 314 Mbps |
| Altera | Cyclone V | C6 | 754 | 595 | 2048 bits | 262 MHz | 435 Mbps |
| Altera | Arria II GX | I3 | 714 | 797 | 2048 bits | 260 MHz | 432 Mbps |
Methodology notes:
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Synthesis results were obtained using the freely available versions of Xilinx ISE and Altera Quartus environments, with speed optimization efforts set to high.
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Maximum frequency is that reported by Synthesis for Xilinx ISE, and TimeQuest's Slowest V/T model for Altera Quartus.
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Maximum throughput refers to AES128 and is calculated as: Max. frequency x 128 bits per block / 77 cycles per block.
Support
Included with the core is:
- Technical support via email
- IP Core Datasheet
- Instantiation Template
- Complete Testbench for source code
For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.