VISENGI's H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. It currently is the only H.264 encoder permitting UltraHD 4K 60 on low-range FPGAs and 8K 30 on mid-range Arria 10 and Zynq 7030 FPGAs.
VISENGI offers two encoder variants to meet the different targets of features, resource usage, and compression:
- H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression. It does not require external memory.
- H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression.
Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.
The main features of the H.264 Encoders are:
Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.
INDUSTRY'S HIGHEST SPEED constant throughput of 5.2 pixels encoded per clock cycle (0.19 clk/pix).
SINGLE ENGINE, resulting in the lowest possible latency, as opposed to multi-engine solutions.
Achieves 8K 30 fps on mid-range Altera Arria 10 and Xilinx Zynq 7030 FPGAs
Achieves UltraHD 4K 60 fps on low-end and low-cost Artix-7 and Cyclone V FPGAs
Up to 32 inputs encoded in parallel with a single instance
Unlimited resolutions supported, from QVGA to 8K and beyond with the same IP core.
Realtime configurable VBR/CBR mode (Variable/Constant Bit Rate) automatically controls all H.264 parameters.
Very low latency (16 lines' time) from first pixel input.
High 4:4:4 Predictive Profile (H264E-P) and CAVLC 4:4:4 Intra Profile (H264E-I and H264E-P).
UltraHD 4K 60 level (5.2) resolution allowed by H.264 standard at just 102 MHz (most low- and mid-range FPGAs).
Optionally encode beyond the maximum level (currently 6.2) to handle future H.264 specification's revisions.
Preserves full color fidelity with color subsampling 4:4:4 (4:2:2 and 4:2:0 inputs allowed too).
Selectable number of predicted frames (P) per keyframe (I) on H264E-P.
Selectable number of slices per frame: from one slice per frame to one slice for every 16 lines.
Output in Byte stream format (raw .264) for easier encapsulation.
(H264E-P) Full reconstructed video preview output.
(H264E-I) Optional pseudo-reconstructed video preview output.
Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
Optional optimized pixel input mode to boost shared memory efficiency.
The data interfaces in the H.264 Encoder IP Core (H264E) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
The input/output interfaces of the H264E IP core are the following:
Configuration Interface: AXI-Lite slave with a 32 bits interface and 16 registers to control all the necessary parameters of encoding.
Data I/O Interface: AXI3/4 Master interface with a data width of 128 bits for reading input pixels and writing H.264 encoded files from/to memory. Optional AXI4-Stream pixel input interface and AXI4-Stream coded video output.
H264E-P Reconstructed I/O Interface: (H264E-P only) AXI3/4 Master interface with a data width of 128 bits, for reading/writing reconstructed frames.
Interrupt outputs: Two rising-edge interrupts are available, one signals a frame has been processed, and the other that video compression has finished.
Interactive Evaluation Demo Video
Smallest FPGAs running H264E-P at common video modes
VISENGI's H264E-I and H264E-P's careful engineering not only encodes >5.2 pixels per clock cycle, it is also crafted to synthesize at higher clock frequencies than competitors' solutions. The result opens the world of 8K and Ultra HD 4K H264 encoding for FPGAs!
|Standard||Width x Height||Min. Pixel Throughput||Min. H264E Frequency||Smallest FPGA for H264E freq|
|HD 720p30||1280 x 720||28 Mpix/s||6 MHz||Spartan-6|
|HD 720p60||1280 x 720||56 Mpix/s||12 MHz||Spartan-6|
|FullHD 1080p30||1920 x 1080||63 Mpix/s||13 MHz||Spartan-6|
|FullHD 1080p60||1920 x 1080||125 Mpix/s||25 MHz||Spartan-6|
|UltraHD 4K 30||3840 x 2160||249 Mpix/s||48 MHz||Spartan-6|
|UltraHD 4K 60||3840 x 2160||498 Mpix/s||96 MHz||Artix-7 / Cyclone V|
|8K 30||7680 x 4320||996 Mpix/s||192 MHz||Zynq-7030 / Arria 10|
The actual input resolution is user-configurable and not limited to the ones listed above.
H264E-P Resource Usage
In the next table you can find the synthesis results several FPGA vendors and families in which the core may be fitted. Please note that, since our designs are vendor and device independent, if your exact FPGA can not be found but it has enough resources compared to another FPGA, then it will doubtlessly also fit. In any case, if you would like to know the precise and up to date synthesis results for your specific FPGA or for ASIC targets, please contact us with your specific target.
|Xilinx||Virtex-6||-1||44K||54K||32||122||96 MHz||501 Mpix/s||4K60|
|Xilinx||Zynq 7030||-1||44K||54K||32||122||166 MHz||867 Mpix/s||8K25|
|Xilinx||Zynq 7030||-2||44K||54K||32||122||200 MHz||1044 Mpix/s||8K30|
|Xilinx||Zynq 7030||-3||44K||54K||32||122||230 MHz||1201 Mpix/s||8K35|
|Xilinx||Artix-7||-1||44K||54K||32||122||100 MHz||522 Mpix/s||4K60|
|Xilinx||Artix-7||-2||44K||54K||32||122||124 MHz||647 Mpix/s||4K75|
|Xilinx||Artix-7||-3||44K||54K||32||122||140 MHz||731 Mpix/s||4K85|
|Xilinx||Kintex-7||-1||44K||54K||32||122||166 MHz||867 Mpix/s||8K25|
|Xilinx||Kintex-7||-2||44K||54K||32||122||200 MHz||1044 Mpix/s||8K30|
|Xilinx||Kintex-7||-3||44K||54K||32||122||230 MHz||1201 Mpix/s||8K35|
|Xilinx||Spartan-6||-2||44K||66K||32||139||52 MHz||271 Mpix/s||4K30|
|Xilinx||Spartan-6||-3||44K||66K||32||139||61 MHz||318 Mpix/s||4K35|
|Altera||Cyclone III||C7||44K||70K||64||1.8 Mbit||0 MHz||0 Mpix/s|
|Altera||Cyclone IV||C7||44K||70K||64||1.8 Mbit||0 MHz||0 Mpix/s|
|Altera||Cyclone V||C6||44K||35K||32||1.8 Mbit||120 MHz||626 Mpix/s||4K75|
|Altera||Cyclone V||C7||44K||35K||32||1.8 Mbit||100 MHz||522 Mpix/s||4K60|
|Altera||Cyclone V||C8||44K||35K||32||1.8 Mbit||85 MHz||444 Mpix/s||4K50|
|Altera||Arria V||I3||44K||35K||32||1.8 Mbit||150 MHz||783 Mpix/s||4K90|
|Altera||Arria V||C5||44K||35K||32||1.8 Mbit||128 MHz||668 Mpix/s||4K80|
|Altera||Arria 10||I2||44K||35K||32||1.8 Mbit||210 MHz||1097 Mpix/s||8K30|
|Altera||Arria 10||I1||44K||35K||32||1.8 Mbit||240 MHz||1253 Mpix/s||8K35|
|Altera||Stratix IV||C2||44K||50K||64||1.8 Mbit||148 MHz||773 Mpix/s||4K90|
|Altera||Stratix V||C1||44K||35K||32||1.8 Mbit||186 MHz||971 Mpix/s||8K25|
Practical and methodology notes:
Standalone H264E-P IP core with AXI3 interfaces, 4K support, and max. compression. Smaller configurations available (less compression).
Results were obtained using the freely available versions of Xilinx Vivado and Altera Quartus environments.
Resource usage is subject to small changes due to further developments in quality/compression ratio.
Maximum frequency is that reported by Implementation for Xilinx Vivado, and by TimeQuest's Slowest V/T model for Altera Quartus.
Results obtained on bigger device sizes to avoid routing congestion. Frequency may be lower if used on a system with very high resource utilization.
Altera warns: timing characteristics of Arria 10 devices are preliminary (as of Quartus 15.1).
Constant Throughput of the H264 Encoder is: Max. frequency x 256 pixels per MB / 49 cycles per MB.
- Technical support via email
- IP Core Datasheet
- Xilinx Vivado drag'n'drop instance
- Altera Qsys drag'n'drop instance
- Linux driver for embedded setups
- Example SW control application
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