This hardware IP core is a ZBT SRAM controller capable of automatically managing single address and full continuous burst read/writes to ZBT SRAM memory chips.
- Customizable to any ZBT SRAM memory chip combination.
- Customizable to any FPGA bus (Wishbone, AMBA, OPB, etc.).
- Continuous burst reads/writes.
- Single cycle reads/writes.
- Individual byte enables.
Typical burst access waveform from a Wishbone bus device:
Included with the core is:
- Technical support via email
- IP Core Datasheet
- Instantiation Template
- Complete Testbench for source code
For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.